1. Field of the Invention
The present invention relates to a phase synchronization circuit that generates an output signal synchronous with a reference signal in both frequency and phase, and to a receiver that incorporates this phase synchronization circuit.
2. Description of the Related Art
Phase synchronization circuits that can generate an output signal synchronous with a reference signal in frequency and phase are well known as phase locked loops (PLLs). An exemplary PLL includes a voltage-controlled oscillator (VCO), a phase detector, an analog filter, and an amplifier. The VCO has its oscillation frequency controlled by the control voltage applied to it. The phase detector detects the phase difference between the reference signal and the output signal of the VCO. The analog filter suppresses unnecessary waves of the output signal of the phase detector. The amplifier amplifies the output signal of the analog filter, producing an output signal.
The PLL is not limited to an analog type. It may be a digital type. R. Staszewski, “All-Digital PLL and Transmitter for Mobile Phones”, IEEE J. of Solid-State Circuits Vol. 40, No. 12, December 2005 (hereinafter referred to as “related art”) discloses a digital PLL. This digital PLL includes a VCO, a time-to-digital converter (TDC), a digital filter, and a digital-to-analog converter (DAC). The TDC detects the frequency difference and phase difference between the reference signal and the output signal of the VCO, and output a digital detection signal based on the frequency difference and phase difference. The digital filter suppresses unnecessary waves of the digital detection signal. The DAC converts the output signal of the digital filter to an analog voltage, which controls the VCO. In many analog PLL, the analog filter has an external capacitor. In many digital PLL, not an analog filter, but an on-chip digital filter is used. The digital PLL can therefore be configured to have a smaller area than the analog PLL.
However, the TDC generates quantization noise, however. This is inevitable, because the TDC converts the frequency difference and phase difference to a digital detection signal. Since its resolution is limited, the TDC generates quantization noise equivalent to one least significant bit (LSB) even if the PLL is locked (synchronized) condition. The transfer function valid until the PLL outputs the quantization noise is a low-pass type, and the cut-off frequency depends on the loop band. On the other hand, the transfer function valid until the PLL outputs the phase noise the VCO produces is a high-pass type, and the cut-off frequency depends on the loop band. Hence, if the loop band is set to a narrow one in order to suppress the quantization noise, the phase noise of the VCO will hardly be suppressed. Conversely, if the loop band is set to a wide one in order to suppress the phase noise of the VCO, the quantization noise will hardly be suppressed.
JP-A 2004-312726 (KOKAI) describes a double-loop PLL that comprises a digital loop and an analog loop for achieving frequency synchronization and phase synchronization, respectively. In the PLL described in JP-A 2004-312726 (KOKAI), the digital loop has a relatively narrow band, removing quantization noise, whereas the band of the analog loop is relatively wide, removing the phase noise of the VCO.
Any PLL incorporates a phase detector or a phase frequency detector, one of which cannot phase differences smaller than a specific lower limit. The range of phase difference, over which the phase detector cannot detect phase differences, is called the “dead zone.” The dead zone results from the logic delay inherent to the phase detector, and may degrade the phase-noise characteristic of the entire PLL.
JP-A 2004-357076 (KOKAI) describes the circuit configuration of a phase detector designed to avoid the occurrence of a dead zone. In the circuit configuration described in JP-A 2004-357076 (KOKAI), two phase frequency comparators and a plurality of inverters (delay elements) are so combined that the phase difference between the reference signal and the output signal of the VCO may be detected even if they coincide in phase(i.e. the phase difference=0 ).
The double-loop PLL described in JP-A 2004-312726 (KOKAI) is similar to the conventional PLL in that the analog loop performs the phase synchronization. Therefore, the loop band cannot be widened over the maximum value (e.g., 1/10 of the reference signal frequency) possible with the conventional PLL. Further, in this PLL an external capacitor must be used to constitute an analog filter, in order to attain high capacitance. Consequently, the area of the circuit can hardly be reduced, as in the conventional analog-type PLL.
Moreover, the phase detector described in JP-A 2004-357076 (KOKAI) needs to have more delay elements than the ordinary phase detector. The delays these delay elements provide lower the operating stability, i.e., phase margin, of the PLL incorporating the phase detector. To make the matters worse, the reference signal may be superposed with noise, because it is delayed by a plurality of inverters. Further, some margin must be applied to the delay of the reference signal, in view of the process variation, the fluctuation of the power-supply voltage and the temperature dependency of the parameters of the circuit components. The phase detector described in JP-A 2004-357076 (KOKAI) is therefore disadvantageous in terms of power consumption and circuit area, with respect to the entire chip.